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» Abridged addressing: a low power memory addressing strategy
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IBMRD
2006
63views more  IBMRD 2006»
13 years 7 months ago
Decomposing the load-store queue by function for power reduction and scalability
Because they are based on large content-addressable memories, load-store queues (LSQ) present implementation challenges in superscalar processors, especially as issue width and nu...
Lee Baugh, Craig B. Zilles
ARCS
2004
Springer
13 years 11 months ago
STAFF: State Transition Applied Fast Flash Translation Layer
Abstract. Recently, flash memory is widely used in embedded applications since it has strong points: non-volatility, fast access speed, shock resistance, and low power consumption....
Tae-Sun Chung, Stein Park, Myung-Jin Jung, Bumsoo ...
INFOCOM
2005
IEEE
14 years 1 months ago
IPStash: a set-associative memory approach for efficient IP-lookup
—IP-Lookup is a challenging problem because of the increasing routing table sizes, increased traffic, and higher speed links. These characteristics lead to the prevalence of hard...
Stefanos Kaxiras, Georgios Keramidas
ANCS
2009
ACM
13 years 5 months ago
Progressive hashing for packet processing using set associative memory
As the Internet grows, both the number of rules in packet filtering databases and the number of prefixes in IP lookup tables inside the router are growing. The packet processing e...
Michel Hanna, Socrates Demetriades, Sangyeun Cho, ...
VLSID
2007
IEEE
206views VLSI» more  VLSID 2007»
14 years 7 months ago
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...