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MIDDLEWARE
2001
Springer
14 years 2 months ago
Thread Transparency in Information Flow Middleware
Abstract. Existing middleware is based on control-flow centric interaction models such as remote method invocations, poorly matching the structure of applications that process con...
Rainer Koster, Andrew P. Black, Jie Huang, Jonatha...
TACAS
2009
Springer
212views Algorithms» more  TACAS 2009»
14 years 4 months ago
Semantic Reduction of Thread Interleavings in Concurrent Programs
Abstract. We propose a static analysis framework for concurrent programs based on reduction of thread interleavings using sound invariants on the top of partial order techniques. S...
Vineet Kahlon, Sriram Sankaranarayanan, Aarti Gupt...
LCPC
2001
Springer
14 years 2 months ago
The Structure of a Compiler for Explicit and Implicit Parallelism
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
Seon Wook Kim, Rudolf Eigenmann
DSD
2010
IEEE
172views Hardware» more  DSD 2010»
13 years 10 months ago
Adaptive Cache Memories for SMT Processors
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
Sonia López, Oscar Garnica, David H. Albone...
ERSA
2006
186views Hardware» more  ERSA 2006»
13 years 11 months ago
The Case for High Level Programming Models for Reconfigurable Computers
In this paper we first outline and discuss the issues of currently accepted computational models for hybrid CPU/FPGA systems. Then, we discuss the need for researchers to develop ...
David L. Andrews, Ron Sass, Erik Anderson, Jason A...