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DATE
2009
IEEE
159views Hardware» more  DATE 2009»
14 years 4 months ago
Design and implementation of a database filter for BLAST acceleration
— BLAST is a very popular Computational Biology algorithm. Since it is computationally expensive it is a natural target for acceleration research, and many reconfigurable archite...
Panagiotis Afratis, Constantinos Galanakis, Euripi...
CHES
2009
Springer
162views Cryptology» more  CHES 2009»
14 years 10 months ago
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
Jean-Luc Beuchat, Jérémie Detrey, Ni...
LATINCRYPT
2010
13 years 8 months ago
Accelerating Lattice Reduction with FPGAs
We describe an FPGA accelerator for the Kannan–Fincke– Pohst enumeration algorithm (KFP) solving the Shortest Lattice Vector Problem (SVP). This is the first FPGA implementati...
Jérémie Detrey, Guillaume Hanrot, Xa...
GRAPHICSINTERFACE
2001
13 years 11 months ago
Accelerated Splatting using a 3D Adjacency Data Structure
We introduce a new acceleration to the standard splatting volume rendering algorithm. Our method achieves full colour (32-bit), depth-sorted and shaded volume rendering significan...
Jeff Orchard, Torsten Möller
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
14 years 6 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...