36 search results - page 5 / 8 » Accelerating Architectural Simulation by Parallel Execution ... |
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
IAJIT
2010
13 years 5 months ago
2010
: A new code sign implementation of vector median rational hybrid filter based on efficient hardware/software implementation is introduced and applied to colour image filtering pro...
PPOPP
2006
ACM
14 years 1 months ago
2006
ACM
This work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology...
PC
2007
13 years 6 months ago
2007
We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate con...
CLUSTER
2009
IEEE
13 years 5 months ago
2009
IEEE
With the advent of high-performance COTS clusters, there is a need for a simple, scalable and faulttolerant parallel programming and execution paradigm. In this paper, we show that...