Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks

As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for chip multiprocessors (CMPs). However, it is inevitable to suffer from high communication latency due to the increasing number of hops. In this paper, we attempt to accelerate network communication by exploiting communication temporal locality with minimal additional hardware cost in the existing state-of-the-art router architecture. We observe that packets frequently traverse through the same path chosen by previous packets due to repeated communication patterns, such as frequent pair-wise communication. Motivated by our observation, we propose a pseudo-circuit scheme. With previous communication patterns, the scheme reserves crossbar connections creating pseudocircuits, sharable partial circuits within a single router. It reuses the previous arbitration information to bypass switch arbitration if the next fl...

• Type: Journal
• Year: 2010
• Where: MICRO
• Authors: Minseon Ahn, Eun Jung Kim
• Keywords: Communication, Communication Patterns, Hardware, MICRO 2010, State-of-the-art Router Architecture