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» Accelerating SIFT on parallel architectures
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DAC
2002
ACM
14 years 9 months ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik
SIGOPS
2011
215views Hardware» more  SIGOPS 2011»
13 years 3 months ago
Log-based architectures: using multicore to help software behave correctly
While application performance and power-efficiency are both important, application correctness is even more important. In other words, if the application is misbehaving, it is li...
Shimin Chen, Phillip B. Gibbons, Michael Kozuch, T...
ASPLOS
2008
ACM
13 years 10 months ago
Merge: a programming model for heterogeneous multi-core systems
In this paper we propose the Merge framework, a general purpose programming model for heterogeneous multi-core systems. The Merge framework replaces current ad hoc approaches to p...
Michael D. Linderman, Jamison D. Collins, Hong Wan...
MICRO
2010
IEEE
172views Hardware» more  MICRO 2010»
13 years 6 months ago
Architectural Support for Fair Reader-Writer Locking
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
Enrique Vallejo, Ramón Beivide, Adriá...
HPCA
2009
IEEE
14 years 3 months ago
Reconciling specialization and flexibility through compound circuits
While parallelism and multi-cores are receiving much attention as a major scalability path, customization is another, orthogonal and complementary, scalability path which can targ...
Sami Yehia, Sylvain Girbal, Hugues Berry, Olivier ...