481 search results - page 5 / 97 » Acceleration of behavioral simulation on simulation specific... |
ICPP
2009
IEEE
14 years 2 months ago
2009
IEEE
Parallel simulation is a technique to accelerate microarchitecture simulation of CMPs by exploiting the inherent parallelism of CMPs. In this paper, we explore the simulation para...
IISWC
2008
IEEE
14 years 1 months ago
2008
IEEE
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
IJCNN
2000
IEEE
13 years 11 months ago
2000
IEEE
: Conventional hardware platforms are far from reaching real-time simulation requirements of complex spiking neural networks (SNN). Therefore we designed an accelerator board with ...
C5
2003
IEEE
14 years 20 days ago
2003
IEEE
A machine cycle CPU simulator is developed on the Squeak environment for educational use. The developed simulator is able to show hardware behavior in CPU at each system clock. An...
WSC
2008
13 years 9 months ago
2008
This paper presents PiDES, a formalism for discrete event simulation based on Pi-calculus. PiDES provides a rigorous semantics of behavior modeling and coordination for simulation...