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CODES
2007
IEEE
14 years 3 months ago
Predator: a predictable SDRAM memory controller
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
Benny Akesson, Kees Goossens, Markus Ringhofer
DICTA
2003
13 years 10 months ago
Real-Time Detection, Registration and Recognition Using Pixel-Level Fusion of Active/Passive Imagery
  -  A  system  has  been  developed  whereby  active  ladar  and  passive  electro-optic  imaging  data  are  aligned  in  hardware  at  the  pixel  level. ...
Alan Steinberg, Robert Pack
IPPS
2010
IEEE
13 years 7 months ago
A lock-free, cache-efficient multi-core synchronization mechanism for line-rate network traffic monitoring
Line-rate data traffic monitoring in high-speed networks is essential for network management. To satisfy the line-rate requirement, one can leverage multi-core architectures to par...
Patrick P. C. Lee, Tian Bu, Girish P. Chandranmeno...
TIME
2005
IEEE
14 years 2 months ago
LOLA: Runtime Monitoring of Synchronous Systems
Abstract— We present a specification language and algorithms for the online and offline monitoring of synchronous systems including circuits and embedded systems. Such monitori...
Ben D'Angelo, Sriram Sankaranarayanan, Césa...
ICSE
2007
IEEE-ACM
14 years 9 months ago
The CRUTIAL Architecture for Critical Information Infrastructures
Abstract. In this chapter we discuss the susceptibility of critical information infrastructures to computer-borne attacks and faults, mainly due to their largely computerized natur...
Paulo Veríssimo, Nuno Ferreira Neves, Migue...