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ISCA
1997
IEEE
119views Hardware» more  ISCA 1997»
14 years 2 months ago
The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference
Deeply pipelined, superscalar processors require accurate branch prediction to achieve high performance. Two-level branch predictors have been shown to achieve high prediction acc...
Eric Sprangle, Robert S. Chappell, Mitch Alsup, Ya...
CONEXT
2008
ACM
14 years 6 days ago
Distributed content delivery using load-aware network coordinates
To scale to millions of Internet users with good performance, content delivery networks (CDNs) must balance requests between content servers while assigning clients to nearby serv...
Nicholas Ball, Peter R. Pietzuch
EUROPAR
2008
Springer
14 years 5 days ago
Data Mining Algorithms on the Cell Broadband Engine
The Cell Broadband Engine (CBE) is a new heterogeneous multi-core processor from IBM, Sony and Toshiba, and provides the potential to achieve an impressive level of performance for...
Rubing Duan, Alfred Strey
NAACL
2003
13 years 11 months ago
Language and Task Independent Text Categorization with Simple Language Models
We present a simple method for language independent and task independent text categorization learning, based on character-level n-gram language models. Our approach uses simple in...
Fuchun Peng, Dale Schuurmans, Shaojun Wang
PICS
2003
13 years 11 months ago
Level-Successive Encoding for Digital Photography
We propose a level-successive encoding scheme for the compression of continuous tone images. The compressed bit stream is partitioned into individual segments corresponding to suc...
Mehmet Utku Celik, Gaurav Sharma, A. Murat Tekalp