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IEEEINTERACT
2002
IEEE
14 years 1 months ago
On the Predictability of Program Behavior Using Different Input Data Sets
Smaller input data sets such as the test and the train input sets are commonly used in simulation to estimate the impact of architecture/micro-architecture features on the perform...
Wei-Chung Hsu, Howard Chen, Pen-Chung Yew, Dong-yu...
ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
14 years 1 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
ICS
2010
Tsinghua U.
13 years 10 months ago
Timing local streams: improving timeliness in data prefetching
Data prefetching technique is widely used to bridge the growing performance gap between processor and memory. Numerous prefetching techniques have been proposed to exploit data pa...
Huaiyu Zhu, Yong Chen, Xian-He Sun
INFOCOM
2007
IEEE
14 years 3 months ago
Performance of Random Access Scheduling Schemes in Multi-Hop Wireless Networks
Abstract— The performance of scheduling schemes in multihop wireless networks has attracted significant attention in the recent literature. It is well known that optimal schedul...
Changhee Joo, Ness B. Shroff
FPL
2006
Springer
85views Hardware» more  FPL 2006»
14 years 12 days ago
High-Performance and Parameterized Matrix Factorization on FPGAs
FPGAs have become an attractive choice for scientific computing. In this paper, we propose a high performance design for LU decomposition, a key kernel in many scientific and engi...
Ling Zhuo, Viktor K. Prasanna