ISCA 2000 - PDF Preprint Papers

ISCA 2000 International Symposium on Computer Architecture

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ISCA
2000
IEEE

156views Hardware» more ISCA 2000»

CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit

14 years 4 months ago

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Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...

Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...

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Id	Views	Title	Status

1	156	CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit	claim
2	134	Architectural support for scalable speculative parallelization in shared-memory multiprocessors	claim
3	121	Selective, accurate, and timely self-invalidation using last-touch prediction	claim
4	121	Memory access scheduling	claim
5	118	Smart Memories: a modular reconfigurable architecture	claim
6	117	Wattch: a framework for architectural-level power analysis and optimizations	claim
7	111	HLS: combining statistical and symbolic simulation to guide microprocessor designs	claim
8	111	Understanding the backward slices of performance degrading instructions	claim
9	107	A fully associative software-managed cache design	claim
10	105	Multiple-banked register file architectures	claim
11	103	Piranha: a scalable architecture based on single-chip multiprocessing	claim
12	103	Circuits for wide-window superscalar processors	claim
13	99	Transient fault detection via simultaneous multithreading	claim
14	97	Energy-driven integrated hardware-software optimizations using SimplePower	claim
15	94	A hardware mechanism for dynamic extraction and relayout of program hot spots	claim
16	93	Reconfigurable caches and their application to media processing	claim
17	92	Trace preconstruction	claim
18	91	Performance analysis of the Alpha 21264-based Compaq ES40 system	claim
19	90	A scalable approach to thread-level speculation	claim
20	81	Clock rate versus IPC: the end of the road for conventional microarchitectures	claim
21	78	On the value locality of store instructions	claim
22	78	Vector instruction set support for conditional operations	claim
23	63	An embedded DRAM architecture for large-scale spatial-lattice computations	claim

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