1427 search results - page 14 / 286 » Achieving High Performance with FPGA-Based Computing |
CLUSTER
2006
IEEE
14 years 2 months ago
2006
IEEE
As new processor and memory architectures advance, clusters start to be built from larger SMP systems, which makes MPI intra-node communication a critical issue in high performanc...
CCGRID
2006
IEEE
14 years 10 days ago
2006
IEEE
MPICH2 provides a layered architecture for implementing MPI-2. In this paper, we provide a new design for implementing MPI-2 over InfiniBand by extending the MPICH2 ADI3 layer. Ou...
DAC
1996
ACM
14 years 23 days ago
1996
ACM
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a c...
SBACPAD
2008
IEEE
14 years 3 months ago
2008
IEEE
This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...
PPOPP
1995
ACM
14 years 4 days ago
1995
ACM
Scalable busy-wait synchronization algorithms are essential for achieving good parallel program performance on large scale multiprocessors. Such algorithms include mutual exclusio...