Sciweavers

1427 search results - page 47 / 286
» Achieving High Performance with FPGA-Based Computing
Sort
View
IEEEPACT
2002
IEEE
14 years 1 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
ISCC
2002
IEEE
131views Communications» more  ISCC 2002»
14 years 1 months ago
Scheduling real time parallel structure on cluster computing
: - Efficient task scheduling is essential for achieving high performance computing applications for distributed systems. Most of existing real-time systems consider schedulability...
Reda A. Ammar, Abdulrahman Alhamdan
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
14 years 3 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie
SDM
2009
SIAM
184views Data Mining» more  SDM 2009»
14 years 5 months ago
DensEst: Density Estimation for Data Mining in High Dimensional Spaces.
Subspace clustering and frequent itemset mining via “stepby-step” algorithms that search the subspace/pattern lattice in a top-down or bottom-up fashion do not scale to large ...
Emmanuel Müller, Ira Assent, Ralph Krieger, S...
ICNP
2007
IEEE
14 years 3 months ago
Identifying High Throughput Paths in 802.11 Mesh Networks: a Model-based Approach
Abstract— We address the problem of identifying high throughput paths in 802.11 wireless mesh networks. We introduce an analytical model that accurately captures the 802.11 MAC p...
Theodoros Salonidis, Michele Garetto, A. Saha, Edw...