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» Achieving High Performance with FPGA-Based Computing
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HOTI
2005
IEEE
14 years 2 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
ICS
2005
Tsinghua U.
14 years 2 months ago
Automatic generation and tuning of MPI collective communication routines
In order for collective communication routines to achieve high performance on different platforms, they must be able to adapt to the system architecture and use different algori...
Ahmad Faraj, Xin Yuan
SASP
2008
IEEE
162views Hardware» more  SASP 2008»
14 years 3 months ago
Accelerating Compute-Intensive Applications with GPUs and FPGAs
—Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are F...
Shuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadr...
CCGRID
2001
IEEE
14 years 11 days ago
XtremWeb: A Generic Global Computing System
Global Computing achieves high throughput computing by harvesting a very large number of unused computing resources connected to the Internet. This parallel computing model target...
Gilles Fedak, Cécile Germain, Vincent N&eac...
NOCS
2010
IEEE
13 years 6 months ago
Design of a High-Throughput Distributed Shared-Buffer NoC Router
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...
Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin,...