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ICLP
2007
Springer
14 years 2 months ago
User-Definable Resource Bounds Analysis for Logic Programs
We present a static analysis that infers both upper and lower bounds on the usage that a logic program makes of a set of user-definable resources. The inferred bounds will in gener...
Jorge Navas, Edison Mera, Pedro López-Garc&...
ATVA
2006
Springer
131views Hardware» more  ATVA 2006»
14 years 2 months ago
Timed Unfoldings for Networks of Timed Automata
Whereas partial order methods have proved their efficiency for the analysis of discrete-event systems, their application to timed systems remains a challenging research topic. Here...
Patricia Bouyer, Serge Haddad, Pierre-Alain Reynie...
DATE
2004
IEEE
184views Hardware» more  DATE 2004»
14 years 2 months ago
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
Panagiotis Manolios, Sudarshan K. Srinivasan
ESORICS
2004
Springer
14 years 2 months ago
Information Flow Control Revisited: Noninfluence = Noninterference + Nonleakage
Abstract. We revisit the classical notion of noninterference for statebased systems, as presented by Rushby in 1992. We strengthen his results in several ways, in particular clarif...
David von Oheimb
FDL
2004
IEEE
14 years 2 months ago
A Formal Verification Approach for IP-based Designs
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
Daniel Karlsson, Petru Eles, Zebo Peng