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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 4 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
ASPLOS
2010
ACM
14 years 2 months ago
CoreDet: a compiler and runtime system for deterministic multithreaded execution
The behavior of a multithreaded program does not depend only on its inputs. Scheduling, memory reordering, timing, and low-level hardware effects all introduce nondeterminism in t...
Tom Bergan, Owen Anderson, Joseph Devietti, Luis C...
PLDI
2009
ACM
14 years 2 months ago
Dynamic software updates: a VM-centric approach
Software evolves to fix bugs and add features. Stopping and restarting programs to apply changes is inconvenient and often costly. Dynamic software updating (DSU) addresses this ...
Suriya Subramanian, Michael W. Hicks, Kathryn S. M...
ICDE
2007
IEEE
134views Database» more  ICDE 2007»
14 years 1 months ago
Outlier Detection for Fine-grained Load Balancing in Database Clusters
Recent industry trends towards reducing the costs of ownership in large data centers emphasize the need for database system techniques for both automatic performance tuning and ef...
Jin Chen, Gokul Soundararajan, Madalin Mihailescu,...
IEEEPACT
2007
IEEE
14 years 1 months ago
The OpenTM Transactional Application Programming Interface
Transactional Memory (TM) simplifies parallel programming by supporting atomic and isolated execution of user-identified tasks. To date, TM programming has required the use of l...
Woongki Baek, Chi Cao Minh, Martin Trautmann, Chri...