144 search results - page 12 / 29 » Adapting cache line size to application behavior |
EH
1999
IEEE
13 years 11 months ago
1999
IEEE
An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16bit address space into an 8-bit one. The target technology is FPGA,...
CSREAESA
2003
13 years 8 months ago
2003
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
TSP
2008
13 years 7 months ago
2008
A new framework for designing robust adaptive filters is introduced. It is based on the optimization of a certain cost function subject to a time-dependent constraint on the norm o...
ISVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
ECRTS
2005
IEEE
14 years 1 months ago
2005
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...