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» Adapting cache line size to application behavior
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ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
14 years 20 days ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
FAST
2010
13 years 9 months ago
quFiles: The Right File at the Right Time
is a unifying abstraction that simplifies data management by encapsulating different physical representations of the same logical data. Similar to a quBit (quantum bit), the parti...
Kaushik Veeraraghavan, Jason Flinn, Edmund B. Nigh...
TC
1998
13 years 7 months ago
Optimizing the Instruction Cache Performance of the Operating System
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
Josep Torrellas, Chun Xia, Russell L. Daigle
IWMM
2004
Springer
90views Hardware» more  IWMM 2004»
14 years 23 days ago
Automatic heap sizing: taking real memory into account
Heap size has a huge impact on the performance of garbage collected applications. A heap that barely meets the application’s needs causes excessive GC overhead, while a heap tha...
Ting Yang, Matthew Hertz, Emery D. Berger, Scott F...
CCR
2004
116views more  CCR 2004»
13 years 7 months ago
End-to-end congestion control for TCP-friendly flows with variable packet size
Current TCP-friendly congestion control mechanisms adjust the packet rate in order to adapt to network conditions and obtain a throughput not exceeding that of a TCP connection op...
Jörg Widmer, Catherine Boutremans, Jean-Yves ...