61 search results - page 12 / 13 » Adaptive Cache Memories for SMT Processors |
ASPLOS
2004
ACM
14 years 1 months ago
2004
ACM
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Dictionary code compression is a technique where long instructions in the memory are replaced with shorter code words used as index in a table to look up the original instructions...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key...
TC
2010
13 years 6 months ago
2010
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
SC
1995
ACM
13 years 11 months ago
1995
ACM
The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...