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MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
14 years 2 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
APPT
2005
Springer
14 years 2 months ago
Static Partitioning vs Dynamic Sharing of Resources in Simultaneous MultiThreading Microarchitectures
Simultaneous MultiThreading (SMT) achieves better system resource utilization and higher performance because it exploits ThreadLevel Parallelism (TLP) in addition to “conventiona...
Chen Liu, Jean-Luc Gaudiot
FPL
2005
Springer
122views Hardware» more  FPL 2005»
14 years 2 months ago
FPGA-Aware Garbage Collection in Java
— During codesign of a system, one still runs into the impedance mismatch between the software and hardware worlds. er identifies the different levels of abstraction of hardware...
Philippe Faes, Mark Christiaens, Dries Buytaert, D...
GECCO
2005
Springer
140views Optimization» more  GECCO 2005»
14 years 2 months ago
CGP visits the Santa Fe trail: effects of heuristics on GP
GP uses trees to represent chromosomes. The user defines the representation space by defining the set of functions and terminals to label the nodes in the trees, and GP searches t...
Cezary Z. Janikow, Christopher J. Mann
IFIP
2005
Springer
14 years 2 months ago
Global Internet Routing Forensics: Validation of BGP Paths Using ICMP Traceback
Nearly all network applications rely on the global Internet routing infrastructure to compute routes and deliver packets. Unfortunately, false Internet routes can be maliciously in...
Eunjong Kim, Daniel Massey, Indrajit Ray
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