Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System

Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware synthesis system where the schedule is used to determine various components of the hardware, including datapath, storage, and interconnect, the goals of a scheduler change drastically. In addition to achieving the traditional goals, the scheduler must proactively make decisions to ensure efficient hardware is produced. This paper proposes two exact solutions for cost sensitive modulo scheduling, one based on an integer linear programming formulation and another based on branch-and-bound search. To achieve reasonable compilation times, decomposition techniques to break down the complex scheduling problem into phase ordered sub-problems are proposed. The decomposition techniques work either by partitioning the dataflow graph into smaller subgraphs and optimally scheduling the subgraphs, or by splitting the s...

• Type: Conference
• Year: 2005
• Where: MICRO
• Authors: Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke
• Keywords: Cost Sensitive Modulo, Hardware, MICRO 2005, Modulo Schedulers, Sensitive Modulo Scheduling