114 search results - page 11 / 23 » Address Register Assignment for Reducing Code Size |
LCPC
2005
Springer
14 years 6 days ago
2005
Springer
Tera-scale high-performance computing has enabled scientists to tackle very large and computationally challenging scientific problems, making the advancement of scientific discov...
FPGA
2007
ACM
14 years 27 days ago
2007
ACM
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
DFT
2004
IEEE
13 years 10 months ago
2004
IEEE
This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output encoder based on check matrix of a (n, n1, m, 3) convolutional...
ICS
2009
Tsinghua U.
14 years 1 months ago
2009
Tsinghua U.
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
SAS
2007
Springer
14 years 25 days ago
2007
Springer
Abstract. Silicon chip design has passed a threshold whereby exponentially increasing transistor density (Moore’s Law) no longer translates into increased processing power for si...