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» Advanced High Performance Algorithms for Data Processing
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GLVLSI
2003
IEEE
310views VLSI» more  GLVLSI 2003»
15 years 9 months ago
54x54-bit radix-4 multiplier based on modified booth algorithm
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-se...
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
15 years 10 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie
252
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LCPC
2005
Springer
15 years 9 months ago
Applying Data Copy to Improve Memory Performance of General Array Computations
Abstract. Data copy is an important compiler optimization which dynamically rearranges the layout of arrays by copying their elements into local buffers. Traditionally, array copy...
Qing Yi
CLEIEJ
2002
113views more  CLEIEJ 2002»
15 years 4 months ago
The MT Stack: Paging Algorithm and Performance in a Distributed Virtual Memory System
Advances in parallel computation are of central importance to Artificial Intelligence due to the significant amount of time and space their programs require. Functional languages ...
Marco T. Morazán, Douglas R. Troeger, Myles...
ANSS
2006
IEEE
15 years 10 months ago
Grid-Boxing for Spatial Simulation Performance Optimisation
— Computer simulations of complex systems such as physical aggregation processes or swarming and collective behaviour of life-forms, often require order N-squared computational c...
Kenneth A. Hawick, Heath A. James, C. J. Scogings