Sciweavers

241 search results - page 23 / 49
» Advanced Loop Optimizations for Parallel Computers
Sort
View
NPC
2010
Springer
13 years 5 months ago
Exposing Tunable Parameters in Multi-threaded Numerical Code
Achieving high performance on today’s architectures requires careful orchestration of many optimization parameters. In particular, the presence of shared-caches on multicore arch...
Apan Qasem, Jichi Guo, Faizur Rahman, Qing Yi
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
14 years 2 months ago
High level H.264/AVC video encoder parallelization for multiprocessor implementation
— H.264/AVC (Advanced Video Codec) is a new video coding standard developed by a joint effort of the ITU-TVCEG and ISO/IEC MPEG. This standard provides higher coding efficiency r...
Hajer K. Zrida, Abderrazek Jemai, Ahmed C. Ammari,...
IPPS
1998
IEEE
13 years 11 months ago
Compiler-Optimization of Implicit Reductions for Distributed Memory Multiprocessors
This paper presents reduction recognition and parallel code generationstrategies for distributed-memorymultiprocessors. We describe techniques to recognize a broad range of implic...
Bo Lu, John M. Mellor-Crummey
ICPPW
2005
IEEE
14 years 1 months ago
Speculative Parallel Threading Architecture and Compilation
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
Xiao-Feng Li, Zhao-Hui Du, Chen Yang, Chu-Cheow Li...
MST
2010
146views more  MST 2010»
13 years 2 months ago
The Cache-Oblivious Gaussian Elimination Paradigm: Theoretical Framework, Parallelization and Experimental Evaluation
We consider triply-nested loops of the type that occur in the standard Gaussian elimination algorithm, which we denote by GEP (or the Gaussian Elimination Paradigm). We present tw...
Rezaul Alam Chowdhury, Vijaya Ramachandran