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CANPC
1999
Springer
15 years 9 months ago
Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...
David Brooks, Margaret Martonosi
134
Voted
USS
2004
15 years 6 months ago
TIED, LibsafePlus: Tools for Runtime Buffer Overflow Protection
Buffer overflow exploits make use of the treatment of strings in C as character arrays rather than as first-class objects. Manipulation of arrays as pointers and primitive pointer...
Kumar Avijit, Prateek Gupta, Deepak Gupta
156
Voted
CODES
2006
IEEE
15 years 11 months ago
Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines
In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylization...
Manjunath Kudlur, Kevin Fan, Scott A. Mahlke
EMSOFT
2011
Springer
14 years 5 months ago
From boolean to quantitative synthesis
Motivated by improvements in constraint-solving technology and by the increase of routinely available computational power, partial-program synthesis is emerging as an effective a...
Pavol Cerný, Thomas A. Henzinger
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
15 years 9 months ago
Selective, accurate, and timely self-invalidation using last-touch prediction
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
An-Chow Lai, Babak Falsafi