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TVLSI
2008
133views more  TVLSI 2008»
13 years 7 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias
CASES
2001
ACM
13 years 11 months ago
The very portable optimizer for digital signal processors
Although retargetability has been a major design concern for many compilers, retargetability is a vitally important issue for Digital Signal Processors(DSPs) because the architect...
Sungjoon Jung, Yunheung Paek
ICCAD
2003
IEEE
138views Hardware» more  ICCAD 2003»
14 years 4 months ago
Multi-Million Gate FPGA Physical Design Challenges
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time du...
Maogang Wang, Abhishek Ranjan, Salil Raje
CF
2010
ACM
14 years 1 months ago
ERBIUM: a deterministic, concurrent intermediate representation for portable and scalable performance
Tuning applications for multi-core systems involve subtle concepts and target-dependent optimizations. New languages are being designed to express concurrency and locality without...
Cupertino Miranda, Philippe Dumont, Albert Cohen, ...
CODES
2006
IEEE
14 years 2 months ago
Fuzzy decision making in embedded system design
The use of Application Specific Instruction-set Processors (ASIP) is a solution to the problem of increasing complexity in embedded systems design. One of the major challenges in...
Alessandro G. Di Nuovo, Maurizio Palesi, Davide Pa...