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FCCM
2007
IEEE
115views VLSI» more  FCCM 2007»
15 years 10 months ago
Generating FPGA-Accelerated DFT Libraries
We present a domain-specific approach to generate highperformance hardware-software partitioned implementations of the discrete Fourier transform (DFT) in fixed point precision....
Paolo D'Alberto, Peter A. Milder, Aliaksei Sandryh...
ICPADS
2006
IEEE
15 years 10 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
144
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ICPP
2005
IEEE
15 years 9 months ago
Two-Tier Resource Allocation for Slowdown Differentiation on Server Clusters
Slowdown, defined as the ratio of a request’s queueing delay to its service time, is accepted as an important quality of service metric of Internet servers. In this paper, we i...
Xiaobo Zhou, Yu Cai, C. Edward Chow, Marijke F. Au...
ITC
2000
IEEE
124views Hardware» more  ITC 2000»
15 years 8 months ago
Wrapper design for embedded core test
A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (T...
Yervant Zorian, Erik Jan Marinissen, Maurice Lousb...
IPPS
1998
IEEE
15 years 8 months ago
Rendering Computer Animations on a Network of Workstations
Rendering high-quality computer animations requires intensive computation, and therefore a large amount of time. One way to speed up this process is to devise rendering algorithms...
Timothy D. Davis, Edward W. Davis