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DATE
2002
IEEE
135views Hardware» more  DATE 2002»
14 years 2 months ago
Reducing Test Application Time Through Test Data Mutation Encoding
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by encoding the bits th...
Sherief Reda, Alex Orailoglu
ITC
1997
IEEE
107views Hardware» more  ITC 1997»
14 years 2 months ago
Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique
The detection of cell stability and data retention faults in SRAMs has been a time consuming process. In this paper we discuss a new design for test technique called Weak Write Tes...
Anne Meixner, Jash Banik
ATS
2004
IEEE
97views Hardware» more  ATS 2004»
14 years 1 months ago
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin N...
ISSRE
2005
IEEE
14 years 3 months ago
Providing Test Quality Feedback Using Static Source Code and Automatic Test Suite Metrics
A classic question in software development is “H ow much testing is enough?” Aside from dynamic coverage-based metrics, there are few measures that can be used to provide guid...
Nachiappan Nagappan, Laurie A. Williams, Jason Osb...
ICST
2008
IEEE
14 years 4 months ago
Relationships between Test Suites, Faults, and Fault Detection in GUI Testing
Software-testing researchers have long sought recipes for test suites that detect faults well. In the literature, empirical studies of testing techniques abound, yet the ideal tec...
Jaymie Strecker, Atif M. Memon