In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by encoding the bits th...
The detection of cell stability and data retention faults in SRAMs has been a time consuming process. In this paper we discuss a new design for test technique called Weak Write Tes...
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin N...
A classic question in software development is “H ow much testing is enough?” Aside from dynamic coverage-based metrics, there are few measures that can be used to provide guid...
Nachiappan Nagappan, Laurie A. Williams, Jason Osb...
Software-testing researchers have long sought recipes for test suites that detect faults well. In the literature, empirical studies of testing techniques abound, yet the ideal tec...