We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Ku...
By extending the system theory under the (min, +) algebra to the time-varying setting, we solve the problem of constrained traffic regulation and develop a calculus for dynamic ser...
Cheng-Shang Chang, Rene L. Cruz, Jean-Yves Le Boud...