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CODES
2006
IEEE
14 years 1 months ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
ANOR
2007
108views more  ANOR 2007»
13 years 7 months ago
Towards a practical engineering tool for rostering
The profitability and morale of many organizations (such as factories, hospitals and airlines) are affected by their ability to schedule their personnel properly. Sophisticated an...
Edward P. K. Tsang, John A. Ford, Patrick Mills, R...
ILP
2005
Springer
14 years 1 months ago
Deriving a Stationary Dynamic Bayesian Network from a Logic Program with Recursive Loops
Recursive loops in a logic program present a challenging problem to the PLP framework. On the one hand, they loop forever so that the PLP backward-chaining inferences would never s...
Yi-Dong Shen, Qiang Yang
AAAI
2006
13 years 9 months ago
DNNF-based Belief State Estimation
As embedded systems grow increasingly complex, there is a pressing need for diagnosing and monitoring capabilities that estimate the system state robustly. This paper is based on ...
Paul Elliott, Brian C. Williams
ICCAD
2001
IEEE
113views Hardware» more  ICCAD 2001»
14 years 4 months ago
The Design and Optimization of SOC Test Solutions
1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique ar...
Erik Larsson, Zebo Peng, Gunnar Carlsson