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DPHOTO
2010
176views Hardware» more  DPHOTO 2010»
13 years 9 months ago
Low-cost space-varying FIR filter architecture for computational imaging systems
Recent research demonstrates the advantage of designing electro-optical imaging systems by jointly optimizing the optical and digital subsystems. The optical systems designed usin...
Guotong Feng, Mohammed Shoaib, Edward L. Schwartz,...
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
14 years 1 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
ASPDAC
2005
ACM
132views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Automatic synthesis and scheduling of multirate DSP algorithms
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousia...
ISCAS
2003
IEEE
144views Hardware» more  ISCAS 2003»
14 years 1 months ago
A flexible global readout architecture for an analogue SIMD vision chip
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
Piotr Dudek
ISCAS
2003
IEEE
123views Hardware» more  ISCAS 2003»
14 years 1 months ago
Fast prototyping of reconfigurable architectures from a C program
Rapid evaluation and design space exploration at the algorithmic level are important issues in the design cycle. In this paper we propose an original area vs delay estimation meth...
Sebastien Bilavarn, Guy Gogniat, Jean Luc Philippe...