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TCAD
2008
112views more  TCAD 2008»
13 years 10 months ago
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
TODAES
2008
115views more  TODAES 2008»
13 years 9 months ago
Automata-based assertion-checker synthesis of PSL properties
Abstract-- Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We ...
Marc Boule, Zeljko Zilic
ICASSP
2009
IEEE
14 years 5 months ago
Layers and layer interfaces in wireless networks
This paper proposes an optimal architecture for wireless networks based on layers and layer interfaces. In the presence of fading the architecture is shown to be optimal. The resu...
Alejandro Ribeiro
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
ICANN
2005
Springer
14 years 3 months ago
Robust Structural Modeling and Outlier Detection with GMDH-Type Polynomial Neural Networks
Abstract. The paper presents a new version of a GMDH type algorithm able to perform an automatic model structure synthesis, robust model parameter estimation and model validation i...
Tatyana I. Aksenova, Vladimir Volkovich, Alessandr...