1180 search results - page 215 / 236 » Alternating Simulation and IOCO |
116
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ISCA
2005
IEEE
15 years 10 months ago
2005
IEEE
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Up to now, system designers have prim...
133
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MICRO
2005
IEEE
15 years 10 months ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
122
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TRIDENTCOM
2005
IEEE
15 years 10 months ago
2005
IEEE
Today’s Internet backbone networking devices need to be tested under realistic traffic conditions at transmission rates of OC-48 and above. While commercially available synthet...
129
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PLDI
2005
ACM
15 years 10 months ago
2005
ACM
We present a new tool, named DART, for automatically testing software that combines three main techniques: (1) automated extraction of the interface of a program with its external...
141
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ASPLOS
2004
ACM
15 years 9 months ago
2004
ACM
Multiple Clock Domain (MCD) processors are a promising future alternative to today’s fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor ...