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ATVA
2007
Springer
108views Hardware» more  ATVA 2007»
14 years 4 months ago
A New Approach to Bounded Model Checking for Branching Time Logics
Abstract. Bounded model checking (BMC) is a technique for overcoming the state explosion problem which has gained wide industrial acceptance. Bounded model checking is typically ap...
Rotem Oshman, Orna Grumberg
FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 4 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
ISPA
2007
Springer
14 years 4 months ago
Binomial Graph: A Scalable and Fault-Tolerant Logical Network Topology
The number of processors embedded in high performance computing platforms is growing daily to solve larger and more complex problems. The logical network topologies must also suppo...
Thara Angskun, George Bosilca, Jack Dongarra
GLVLSI
2006
IEEE
145views VLSI» more  GLVLSI 2006»
14 years 4 months ago
Leakage current starved domino logic
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
Zhiyu Liu, Volkan Kursun
ISCC
2006
IEEE
202views Communications» more  ISCC 2006»
14 years 4 months ago
Fuzzy Logic Congestion Control in TCP/IP Tandem Networks
Network resource management and control is a complex problem that requires robust, possibly intelligent, control methodologies to obtain satisfactory performance. While many Activ...
Chrysostomos Chrysostomou, Andreas Pitsillides