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» Alternative Test Methods Using IEEE 1149.4
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DFT
2000
IEEE
105views VLSI» more  DFT 2000»
14 years 1 months ago
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits
Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: dom...
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang...
ATS
2004
IEEE
116views Hardware» more  ATS 2004»
14 years 25 days ago
Testing for Missing-Gate Faults in Reversible Circuits
Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of rev...
John P. Hayes, Ilia Polian, Bernd Becker
ICDAR
2005
IEEE
14 years 2 months ago
Language Identification of Character Images Using Machine Learning Techniques
In this paper, we propose a new approach for identifying the language type of character images. We do this by classifying individual character images to determine the language bou...
Ying-Ho Liu, Fu Chang, Chin-Chin Lin
ICRA
2009
IEEE
143views Robotics» more  ICRA 2009»
14 years 3 months ago
Least absolute policy iteration for robust value function approximation
Abstract— Least-squares policy iteration is a useful reinforcement learning method in robotics due to its computational efficiency. However, it tends to be sensitive to outliers...
Masashi Sugiyama, Hirotaka Hachiya, Hisashi Kashim...
VTS
2002
IEEE
113views Hardware» more  VTS 2002»
14 years 2 months ago
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
Krishna Sekar, Sujit Dey