Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits

Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: domino logic suffers from several design problems and one of the most notable ones is the charge-sharingproblem. Charge sharing may degrade output voltage level or even cause erroneous output value (named as chargesharing faulr). In this work, wefind that charge-sharingfaults are extremely resistant to scan test. In fact, charge-sharing faults occurring at the border gates cannot be detected by any scan method, due to the missing error caused by early signal arrival time. Further: we show that killing error might happen in charge-sharing fault detectionfor both border gates and non-border gates because of the low-speed testing problem caused again by scan test. We thoroughly investigate both test errors and propose two design-for-testability techniques to efficiently eliminate bothproblems.

• Type: Conference
• Year: 2000
• Where: DFT
• Authors: Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone
• Keywords: DFT 2000, Domino Logic, Domino Logic Design, Scan Test, VLSI