Sciweavers

339 search results - page 28 / 68
» An ADC-BiST scheme using sequential code analysis
Sort
View
114
Voted
ERSA
2006
147views Hardware» more  ERSA 2006»
15 years 4 months ago
Code Partitioning for Reconfigurable High-Performance Computing: A Case Study
In this case study, various ways to partition a code between the microprocessor and FPGA are examined. Discrete image convolution operation with separable kernel is used as the ca...
Volodymyr V. Kindratenko
ICCAD
2000
IEEE
169views Hardware» more  ICCAD 2000»
15 years 7 months ago
Transistor-Level Timing Analysis Using Embedded Simulation
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
Pawan Kulshreshtha, Robert Palermo, Mohammad Morta...
107
Voted
ICASSP
2009
IEEE
15 years 9 days ago
A differential motion estimation method for image interpolation in distributed video coding
Motion estimation methods based on differential techniques proved to be very useful in the context of video analysis, but have a limited employment in classical video compression ...
Marco Cagnazzo, Thomas Maugey, Béatrice Pes...
WCNC
2010
IEEE
15 years 12 days ago
Physical Layer Network Coding with Multiple Antennas
: The two-phase MIMO NC (network coding) scheme can be used to boost the throughput in a two-way relay channel in which nodes are equipped with multiple antennas. The obvious strat...
Shengli Zhang, Soung Chang Liew
134
Voted
CODES
2008
IEEE
15 years 4 months ago
Performance debugging of Esterel specifications
Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based...
Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samar...