ICCAD 2000 - PDF Preprint Papers

ICCAD 2000 International Conference on Computer-Aided Design

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ICCAD
2000
IEEE

188views Hardware» more ICCAD 2000»

Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method

14 years 8 months ago

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— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...

Sungpack Hong, Taewhan Kim

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Id	Views	Title	Status

1	188	Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method	claim
2	171	A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits	claim
3	169	Transistor-Level Timing Analysis Using Embedded Simulation	claim
4	159	ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters	claim
5	153	Slope Propagation in Static Timing Analysis	claim
6	149	Dynamic Response Time Optimization for SDF Graphs	claim
7	148	FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders	claim
8	148	Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design	claim
9	139	UST/DME: A Clock Tree Router for General Skew Constraints	claim
10	139	Efficient Finite-Difference Method for Quasi-Periodic Steady-State and Small Signal Analyses	claim
11	138	Fast Analysis and Optimization of Power/Ground Networks	claim
12	137	Smart Simulation Using Collaborative Formal and Simulation Engines	claim
13	135	Power Optimization of Real-Time Embedded Systems on Variable Speed Processors	claim
14	132	Frequency Domain Analysis of Switching Noise on Power Supply Network	claim
15	124	Deterministic Test Pattern Generation Techniques for Sequential Circuits	claim
16	124	A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis	claim
17	119	Synthesis of Operation-Centric Hardware Descriptions	claim
18	115	Challenges and Opportunities in Broadband and Wireless Communication Designs	claim
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20	110	Computing Phase Noise Eigenfunctions Directly from Steady-State Jacobian Matrices	claim
21	109	Latency-Guided On-Chip Bus Network Design	claim
22	109	General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs	claim
23	104	Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures	claim
24	102	Provably Good Global Buffering Using an Available Buffer Block Plan	claim
25	100	Partial Simulation-Driven ATPG for Detection and Diagnosis of Faults in Analog Circuits	claim
26	100	Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering	claim
27	99	Potential Slack: An Effective Metric of Combinational Circuit Performance	claim
28	99	On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools	claim
29	97	Error Catch and Analysis for Semiconductor Memories Using March Tests	claim
30	96	How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K	claim
31	95	Test of Future System-on-Chips	claim
32	94	Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan	claim
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35	88	DRAGON2000: Standard-Cell Placement Tool for Large Industry Circuits	claim
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37	84	Timing Driven Gate Duplication: Complexity Issues and Algorithms	claim
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39	82	Full-Chip, Three-Dimensional, Shapes-Based RLC Extraction	claim
40	80	A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise	claim
41	78	DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators	claim
42	77	Improving the Proportion of At-Speed Tests in Scan BIST	claim
43	76	An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays	claim
44	75	Incremental CAD	claim
45	74	Simultaneous Gate Sizing and Fanout Optimization	claim
46	73	Simulation and Optimization of the Power Distribution Network in VLSI Circuits	claim
47	72	Wire Reconnections Based on Implication Flow Graph	claim
48	72	Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation	claim
49	69	Observability Analysis of Embedded Software for Coverage-Directed Validation	claim
50	69	Exploring Performance Tradeoffs for Clustered VLIW ASIPs	claim
51	69	Symbolic Debugging Scheme for Optimized Hardware and Software	claim
52	68	Challenges in Physical Chip Design	claim
53	65	Predictable Routing	claim
54	55	Verification of Delta-Sigma Converters Using Adaptive Regression Modeling	claim

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