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ISLPED
1997
ACM
124views Hardware» more  ISLPED 1997»
13 years 12 months ago
Low power high level synthesis by increasing data correlation
With the increasing performance and density of VLSI circuits as well as the popularity of portable devices such as personal digital assistance, power consumption has emerged as an...
Dongwan Shin, Kiyoung Choi
WICSA
2004
13 years 9 months ago
Compositional Generation of Software Architecture Performance QN Models
Early performance analysis based on Queueing Network Models (QNM) has been often proposed to support software designers during the software development process. These approaches a...
Antinisca Di Marco, Paola Inverardi
SI3D
1995
ACM
13 years 11 months ago
The Sort-First Rendering Architecture for High-Performance Graphics
Interactive graphics applications have long been challenging graphics system designers by demanding machines that can provide ever increasing polygon rendering performance. Anothe...
Carl Mueller
HPCA
2006
IEEE
14 years 8 months ago
Efficient instruction schedulers for SMT processors
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
Joseph J. Sharkey, Dmitry V. Ponomarev
ANCS
2008
ACM
13 years 9 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu