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» An Algorithm for Locating Logic Design Errors
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ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
14 years 5 months ago
Soft error reduction in combinational logic using gate resizing and flipflop selection
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
Rajeev R. Rao, David Blaauw, Dennis Sylvester
DATE
2010
IEEE
168views Hardware» more  DATE 2010»
14 years 1 months ago
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
Luca Sterpone, Niccolò Battezzati
TRANSCI
2010
128views more  TRANSCI 2010»
13 years 6 months ago
An Information-Theoretic Sensor Location Model for Traffic Origin-Destination Demand Estimation Applications
To design a transportation sensor network, the decision-maker needs to determine what sensor investments should be made, as well as when, how, where and with what technologies. Th...
Xuesong Zhou, George F. List
ACST
2006
13 years 9 months ago
A combinatorial group testing method for FPGA fault location
Adaptive fault isolation methods based on discrepancyenabled pairwise comparisons are developed for reconfigurable logic devices. By observing the discrepancy characteristics of m...
Carthik A. Sharma, Ronald F. DeMara
ICC
2008
IEEE
137views Communications» more  ICC 2008»
14 years 2 months ago
On the Effect of Localization Errors on Geographic Routing in Sensor Networks
—Recently, network localization systems that are based on inter-node ranges have received significant attention. Geographic routing has been considered an application which can u...
Bo Peng, Rainer Mautz, Andrew H. Kemp, Washington ...