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DSD
2010
IEEE
172views Hardware» more  DSD 2010»
13 years 8 months ago
Adaptive Cache Memories for SMT Processors
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
Sonia López, Oscar Garnica, David H. Albone...
ICS
2000
Tsinghua U.
14 years 3 days ago
Characterizing processor architectures for programmable network interfaces
The rapid advancements of networking technology have boosted potential bandwidth to the point that the cabling is no longer the bottleneck. Rather, the bottlenecks lie at the cros...
Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Bae...
SAMOS
2007
Springer
14 years 2 months ago
On the Problem of Minimizing Workload Execution Time in SMT Processors
Abstract—Most research work on (Simultaneous Multithreading Processors) SMTs focuses on improving throughput and/or fairness, or on prioritizing some threads over others in a wor...
Francisco J. Cazorla, Enrique Fernández, Pe...
DAMON
2007
Springer
14 years 2 months ago
Pipelined hash-join on multithreaded architectures
Multi-core and multithreaded processors present both opportunities and challenges in the design of database query processing algorithms. Previous work has shown the potential for ...
Philip Garcia, Henry F. Korth
IEEEPACT
2007
IEEE
14 years 2 months ago
FAME: FAirly MEasuring Multithreaded Architectures
Nowadays, multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology ...
Javier Vera, Francisco J. Cazorla, Alex Pajuelo, O...