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IEEEPACT
2009
IEEE
14 years 2 months ago
Chainsaw: Using Binary Matching for Relative Instruction Mix Comparison
With advances in hardware, instruction set architectures are undergoing continual evolution. As a result, compilers are under constant pressure to adapt and take full advantage of...
Tipp Moseley, Dirk Grunwald, Ramesh Peri
CGO
2008
IEEE
14 years 1 months ago
Parallel-stage decoupled software pipelining
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...
Easwaran Raman, Guilherme Ottoni, Arun Raman, Matt...
PPOPP
2009
ACM
14 years 8 months ago
Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors
Recent advances in polyhedral compilation technology have made it feasible to automatically transform affine sequential loop nests for tiled parallel execution on multi-core proce...
Muthu Manikandan Baskaran, Nagavijayalakshmi Vydya...
ICS
2007
Tsinghua U.
14 years 1 months ago
Sensitivity analysis for automatic parallelization on multi-cores
Sensitivity Analysis (SA) is a novel compiler technique that complements, and integrates with, static automatic parallelization analysis for the cases when relevant program behavi...
Silvius Rus, Maikel Pennings, Lawrence Rauchwerger
MICRO
1996
IEEE
96views Hardware» more  MICRO 1996»
13 years 11 months ago
Exceeding the Dataflow Limit via Value Prediction
For decades, the serialization constraints imposed by true data dependences have been regarded as an absolute limit--the dataflow limit--on the parallel execution of serial progra...
Mikko H. Lipasti, John Paul Shen