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MTDT
2003
IEEE
100views Hardware» more  MTDT 2003»
14 years 26 days ago
Optimal Spare Utilization in Repairable and Reliable Memory Cores
Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies t...
Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-...
HPCA
2009
IEEE
14 years 8 months ago
Hardware-software integrated approaches to defend against software cache-based side channel attacks
Software cache-based side channel attacks present serious threats to modern computer systems. Using caches as a side channel, these attacks are able to derive secret keys used in ...
Jingfei Kong, Onur Aciiçmez, Jean-Pierre Se...
AOSD
2007
ACM
13 years 11 months ago
An aspect-oriented approach to bypassing middleware layers
The layered architecture of middleware platforms (such as CORBA, SOAP, J2EE) is a mixed blessing. On the one hand, layers provide services such as demarshaling, session management...
Ömer Erdem Demir, Premkumar T. Devanbu, Eric ...
ICCAD
2001
IEEE
91views Hardware» more  ICCAD 2001»
14 years 4 months ago
A System for Synthesizing Optimized FPGA Hardware from MATLAB
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
Malay Haldar, Anshuman Nayak, Alok N. Choudhary, P...
ECRTS
2007
IEEE
14 years 1 months ago
Memory Resource Management for Real-Time Systems
Dynamic memory storage has been widely used for years in computer science. However, its use in real-time systems has not been considered as an important issue, and memory manageme...
Audrey Marchand, Patricia Balbastre, Ismael Ripoll...