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RTAS
2005
IEEE
15 years 11 months ago
Timing Analysis for Sensor Network Nodes of the Atmega Processor Family
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor fam...
Sibin Mohan, Frank Mueller, David B. Whalley, Chri...
CCECE
2006
IEEE
15 years 11 months ago
A QoS Mapping Rule Builder
Although many QoS management architectures have been recently introduced with a lot of advanced features, they have never been widely used in the existing applications due to the ...
Kim Khoa Nguyen, Brigitte Kerhervé, Brigitt...
SC
2009
ACM
16 years 13 days ago
OddCI: on-demand distributed computing infrastructure
The availability of large quantities of processors is a crucial enabler of many-task computing. Voluntary computing systems have proven that it is possible to build computing plat...
Rostand Costa, Francisco V. Brasileiro, Guido Lemo...
DAC
2005
ACM
16 years 6 months ago
Segregation by primary phase factors: a full-wave algorithm for model order reduction
Existing Full-wave Model Order Reduction (FMOR) approaches are based on Expanded Taylor Series Approximations (ETAS) of the oscillatory full-wave system matrix. The accuracy of su...
Thomas J. Klemas, Luca Daniel, Jacob K. White
VLSID
2002
IEEE
138views VLSI» more  VLSID 2002»
16 years 6 months ago
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
Haris Lekatsas, Jörg Henkel