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    DAC
    2009
    ACM
    125views Computer Architecture» more  DAC 2009»
    Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
    14 years 10 months ago
    Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
    Download  cobweb.ecn.purdue.edu
    This paper presents a technique to improve the storage density of spin-torque transfer (STT) magnetoresistive random access memory (MRAM) in the presence of significant magnetic t...
    Wei Xu, Yiran Chen, Xiaobin Wang, Tong Zhang
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    DAC
    2008
    ACM
    138views Computer Architecture» more  DAC 2008»
    Parameterized timing analysis with general delay models and arbitrary variation sources
    14 years 10 months ago
    Parameterized timing analysis with general delay models and arbitrary variation sources
    Download  www.eecg.toronto.edu
    Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
    Khaled R. Heloue, Farid N. Najm
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    DAC
    2008
    ACM
    170views Computer Architecture» more  DAC 2008»
    DeFer: deferred decision making enabled fixed-outline floorplanner
    14 years 10 months ago
    DeFer: deferred decision making enabled fixed-outline floorplanner
    Download  www.public.iastate.edu
    In this paper, we present DeFer -- a fast, high-quality and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a non-slicing floorplan by compacting a slicing fl...
    Jackey Z. Yan, Chris Chu
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    DAC
    2007
    ACM
    131views Computer Architecture» more  DAC 2007»
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    14 years 10 months ago
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    Download  cobweb.ecn.purdue.edu
    This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
    Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
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    DAC
    2005
    ACM
    120views Computer Architecture» more  DAC 2005»
    Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design
    14 years 10 months ago
    Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design
    Download  www.cs.ucr.edu
    In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
    Jungeun Kim, Taewhan Kim
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