1322 search results - page 214 / 265 » An Architecture for Distributed Simulation Games |
SIGMETRICS
2011
ACM
12 years 10 months ago
2011
ACM
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
ICS
2009
Tsinghua U.
14 years 9 days ago
2009
Tsinghua U.
New static source routing algorithms for High Performance Computing (HPC) are presented in this work. The target parallel architectures are based on the commonly used fattree netw...
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
SSDBM
2005
IEEE
14 years 1 months ago
2005
IEEE
Scientific investigations have to deal with rapidly growing amounts of data from simulations and experiments. During data analysis, scientists typically want to extract subsets o...
HIPC
2009
Springer
13 years 5 months ago
2009
Springer
In many-core architectures, memory blocks are commonly assigned to the banks of a NUCA cache by following a physical mapping. This mapping assigns blocks to cache banks in a round-...