239 search results - page 31 / 48 » An Architecture for Kernel-Level Verification of Executables... |
ICPPW
2005
IEEE
14 years 2 months ago
2005
IEEE
Large–scale parallel applications performing global synchronization may spend a significant amount of execution time waiting for the completion of a barrier operation. Conseque...
DAC
2010
ACM
14 years 16 days ago
2010
ACM
With the ever-increasing transistor variability in CMOS technology, it is essential to integrate variation-aware performance analysis into the task allocation and scheduling proce...
PLDI
2012
ACM
11 years 11 months ago
2012
ACM
Modern architectures implement relaxed memory models which may reorder memory operations or execute them non-atomically. Special instructions called memory fences are provided, al...
DAC
2009
ACM
14 years 9 months ago
2009
ACM
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access will result in a definite cache hit or miss. This unpredictabilit...
ML
2002
ACM
13 years 8 months ago
2002
ACM
The execution order of a block of computer instructions on a pipelined machine can make a difference in running time by a factor of two or more. Compilers use heuristic schedulers...