1269 search results - page 84 / 254 » An Architecture for Parallel Topic Models |
151
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TOMACS
1998
15 years 4 months ago
1998
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
133
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IPPS
2005
IEEE
15 years 10 months ago
2005
IEEE
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
143
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EUROPAR
2010
Springer
15 years 5 months ago
2010
Springer
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
146
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PPOPP
2010
ACM
15 years 11 months ago
2010
ACM
In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a singl...
171
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EAGC
2004
Springer
15 years 10 months ago
2004
Springer
In this short paper we examine the integration of three emerging trends in Information Technology (Utility Computing, Grid Computing, and Web Services) into a new Computing paradig...