Abstract--To reduce chip-scale topography variation in Chemical Mechanical Polishing (CMP) process, dummy fill is widely used to improve the layout density uniformity. Previous res...
Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xu...
A key problem that arises in System-on-a-Chip (SOC) designs of today is the Chip-level Clock Tree Synthesis (CCTS). CCTS is done by merging all the clock trees belonging to differ...
High efficiency low voltage DC-DC conversion is a key enabler to the design of power-efficient integrated circuits. Typically a star configuration of the DC-DC converters, where o...
Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics...
Ad hoc networks face the problem of improving networks’ capacity and scalability. The scalability problem can be properly solved through physical hierarchy networking. In this p...