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SIPS
2007
IEEE
14 years 5 months ago
An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...
TSP
2008
82views more  TSP 2008»
13 years 11 months ago
Fully Parallel Stochastic LDPC Decoders
Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) dec...
Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...